Microprocessor 8085 Machine Cycle

Microprocessor 8085

Q: Why, in 8085, Opcode fetch have 4 T-States whereas all other machine cycles have only 3 T-States?

A: When an instruction is about to be executed, the first machine cycle that is performed by 8085 microprocessor is the opcode fetch machine cycle. Before knowing the opcode fetch machine cycle, we have to know what is actually the opcode is. There are 256 different instructions in 8085 microprocessor. Some of them are near about similar. To distinguish between all the 256 instructions, there are 256 different hexadecimal operational codes that is stored in the 8085 memory. Let an instruction be MVI A,23H is about to be executed. The hexadecimal code for  MVI A is 3AH and that is fixed inside the 8085 memory. When the instruction as about to be executed, the programmer or the user will have to give input the 3AH data in the program input. When 8085 reads the input from the user, it first checks whether the input code is actually the opcode /operational code or any user defined data. Generally, the first input that is provided by the user is considered as the operational code for the specific instruction. So, after taking the input form the user, 8085 will jump to the memory where the operational codes are stored. From the memory, 8085 then fetch the operational code and come back to the execution process.

      This is performed by the opcode fetch machine cycle. The opcode fetch machine cycle is depicted below:

                         Memory Location                             Mnemonics                        Opcode
                                  8000H                                      MVI A,23H                         3A H
                                  8001H                                                                                   23 H

         The table for Machine cycle is given below:


Machine Cycle
Status of ,  &

Control Signals
Required
T-States
Opcode Fetch(OF)
0
1
1
RD'=0
4
Memory Read(MR)
0
1
0
RD'=0
3
Memory Write(MW)
0
0
1
WR'=0
3
I/O Read(IOR)
1
1
0
RD'=0
3
I/O Write(IOW)
1
0
1
WR'=0
3

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